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may 2013 ? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 .1 FDMF6824C extra - small, high - performance, high - frequency drmos module fdmf 682 4 c ex tra - small, high - performance, high - frequency drmos module benefits ? ultra - compact 6x 6 mm pqfn, 72 % space - s aving c ompared to c onventional d iscrete s olutions ? fu lly o ptimized s ystem e fficiency ? clean switching w aveform s with m inimal ri nging ? high - c urrent h a ndling features ? over 93 % peak - e fficiency ? high - c urrent h andling : 50 a ? high - performance pqfn copper - clip package ? 3 - s tate 5 v pwm i nput d river ? skip - mode smod# ( low - side gate turn off ) i nput ? thermal w arning f lag for over - t emperature c ondition ? driver o utp ut d isable f unction (disb# p in) ? internal p ull - u p and p ul l - d own for smod # and disb# i nput s , r espectively ? fairchild powertrench ? t echnology mosfets for c lean v oltag e w aveforms and r educed r inging ? fairchild syncfet ? ( i ntegrated schottky d iode) t e chnology in low - s ide mosfet ? inte grated b ootstrap schottky d iode ? adaptive g ate d rive t imi ng for s hoot - t hrough p rotection ? under - v ol tage l ockout (uvlo) ? optimized for s wi tching fr equencies up to 1 m h z ? low - p rofile smd p ackage ? fairchild green packaging and rohs c ompliance ? based o n the intel ? 4.0 drmos standard description the xs ? drmos family is fairchilds next - generation, fully optimized, ultra - compact, integrated mosfet plus driver power stage solution for high - current, high - frequency , synchronous buck dc - dc applications. th e fdmf 682 4 c integrates a driver ic, two power mosfets , and a bootstrap schottky diode into a thermally enhance d, ultra - compact 6x 6 mm package. with an integrated approach, the complete switching power stage is optimized with regard to driver and mosfet dynamic performance, system inductance, and p ower mosfet r ds(on) . xs ? drmos uses fairchild's high - performance powertrench ? mosfet technology, which dramatically reduces switch ringing, eliminating the need for snubber circuit in most buck converter applications . a driver ic with reduced dead times and propagation delays further enhances the performance. a thermal warning function war n s of a potential over - te mperature situation. the fdmf 682 4 c also incorporates a skip mode ( smod# ) for improved light - load efficiency . the fdmf 682 4 c also provides a 3 - state 5 v pwm input for compatibility with a wide range of pwm controll ers. applications ? high - performance gaming motherboards ? compact blade servers, v - core and non - v - core dc - dc converters ? d esk top computers, v - core and non - v - core dc - dc converters ? workstations ? high - c urrent dc - dc point - of - load c onverters ? networking and t elecom m icroprocessor v oltage r egulators ? small form - f actor voltage r egulator m odules ordering information part number current rating package top mark fdmf 682 4 c 50 a 40 - lead, clipbond pqfn drmos, 6.0 mm x 6.0 mm package fdmf 682 4 c
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 . 1 fdmf6 82 4 c extra - small, high - performance, high - frequency drmos module typical application circuit figure 1. typical application circuit drmos block diagram figure 2. drmos block diagram smod # pwm vcin vdrv vin pgnd phase gh d boot boot gl cgnd disb# thw n# q1 hs power mosfet input 3 - state logic r up_pwm v ci n v ci n uvlo gh logic level - shift dead - t ime control temp. sense 3 0k ? ? gl logic 10a 10a r dn_pwm q2 ls power mosfet vswh v drv 3 0k ? ? v 5 v d i s b # p w m i n p u t o f f o n c v d r v c v i n c b o o t r b o o t l o u t c o u t v i n f d m f 6 8 2 4 c o p e n - d r a i n o u t p u t v d r v v c i n v i n p w m t h w n # b o o t c g n d p g n d d i s b # p h a s e s m o d # c v c i n v o u t v s w h 3 v ~ 1 6 v r v c i n
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 . 1 fdmf6 82 4 c extra - small, high - performance, high - frequency drmos module pin configuration figure 3. bottom view figure 4. top view p in definitions pin # name description 1 smod# when smod # = hi gh , the low - side driver is the inverse of the pwm input. when smod # = l o w , the lo w - side driver is disable d . this pin has a 10 a internal pull - up current source . do not add a noise filter cap acitor . 2 vcin ic b ias s upply. minimum 1 f ceramic capacitor is recommended from this pin to cgnd. 3 vdrv power for the g ate d river. minimum 1 f ceramic capacitor is recommended to be connected as close as possible from this pin to cgnd. 4 boot bootstrap s upply i nput. provides voltage supply to the high - side mosfet driver. connect a bootstrap capacitor from this pin to phase. 5, 37, 41 cgnd ic g round. ground return for driver ic. 6 gh for manufactu ring test only. this pin must float ; it m ust not be connected to any pin. 7 phase switch n ode pin for bootstrap capacitor routing. electrically shorted to vswh pin. 8 nc no c onnect. the pin is not electrically connected internally, but can be connected to vin for convenience. 9 - 14, 42 vin power i nput. output stage supply voltage. 15, 29 - 35, 43 vswh switch n ode i nput. provides return for high - side bootstrapped driver and acts as a sense point for the adapt ive shoot - through protection. 16 C 28 pgnd power g round. output stage ground. source pin of the low - side mosfet . 36 gl for manufacturing test only. this pin must float ; it m ust not be connected to any pin. 38 thw n # thermal w arning f lag, o pen c ollector o utput. when temperature exceeds the trip limit , the output is pulled low . thwn # does n ot disable the module. 39 disb# output d isable. when low , this pin disable s the p ower mos fet switching (gh and gl are held low ). this pin has a 10 a internal pull - down current source . do not add a noise filter capacitor . 40 pwm pwm s ignal i nput. this pin accepts a t hree - state 5 v pwm signal from the controller. 1 2 3 4 5 6 7 8 9 1 0 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 v s w h 4 3 v i n 4 2 c g n d 4 1 s m o d # v c i n v d r v b o o t c g n d g h p h a s e n c v i n v i n v i n v i n v i n v i n v s w h p g n d p g n d p g n d p g n d p g n d v s w h v s w h p g n d p g n d p g n d p g n d p g n d p g n d p g n d p g n d p w m d i s b # t h w n # c g n d g l v s w h v s w h v s w h v s w h v s w h 1 2 3 4 5 6 7 8 9 1 0 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 v s w h 4 3 v i n 4 2 c g n d 4 1 s m o d # v c i n v d r v b o o t c g n d g h p h a s e n c v i n v i n v i n v i n v i n v i n v s w h p g n d p g n d p g n d p g n d p g n d v s w h v s w h p g n d p g n d p g n d p g n d p g n d p g n d p g n d p g n d p w m d i s b # t h w n # c g n d g l v s w h v s w h v s w h v s w h v s w h
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 . 1 fdmf6 82 4 c extra - small, high - performance, high - frequency drmos module absolute maximum ratings stresses exceeding the a bsolute m aximum r atings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating condi tions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v c in supply v oltage referenced to cgnd - 0.3 6 .0 v v drv drive v oltage r eferenced to cgnd - 0.3 6 .0 v v disb# output d isable r eferenced to cgnd - 0.3 6 .0 v v pwm pwm s ignal i nput r eferenced to cgnd - 0.3 6 .0 v v smod# skip m ode i nput r eferenced to cgnd - 0.3 6 .0 v v gl low g ate m anufacturing t est p in r eferenced to cgnd - 0.3 6 .0 v v thwn# thermal w arning f lag r eferenced to cgnd - 0.3 6 .0 v v in power i nput r eferenced to pgnd, cgnd - 0.3 25 .0 v v boot bootstrap s upply referenced to vswh, phase - 0.3 6 .0 v referenced to cgnd - 0.3 25 .0 v v gh high g ate m anufacturing t est p in referenced to vswh, phase - 0.3 6 .0 v referenced to cgnd - 0.3 25 .0 v v phs phase r eferenced to cgnd - 0.3 25 .0 v v swh switch node input referenced to pgnd, cgnd (dc only) - 0.3 25 .0 v referenced to pgnd, <20 ns - 8.0 28 .0 v v boot bootstrap s upply r eferenced to vdrv 2 2 .0 v r eferenced to vdrv , <20 ns 2 5 .0 v i thwn# thwn # sink current - 0.1 7 .0 ma i o(av ) output current ( 1 ) f sw =3 0 0 khz , v in =12 v, v o =1.0 v 50 a f sw =1 mhz , v in =12 v, v o =1.0 v 4 5 jpcb junction - to - pcb thermal resistance 2.7 c / w t a ambient temperature range - 40 +125 c t j maximum junction temperature +150 c t stg storage temperature range - 55 +150 c esd electrostatic discharge protection human body model, jesd22 - a114 2000 v charged device model, jesd22 - c101 2500 note: 1. i o(av) is rated using fairchilds drmos evaluation board, at t a = 25c , with natural convection cooling . this rating is limite d by the peak drmos temperature, t j = 150c, and varies depending on operating conditi ons and pcb layout . this rating can be changed with different application settings . recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend e xceeding them or designing to absolute maximum ratings. symbol parameter min. typ. max. unit v cin control circuit supply voltage 4.5 5 .0 5.5 v v drv gate drive circuit supply voltage 4.5 5 .0 5.5 v v in output stage supply voltage 3 .0 12 .0 1 6 .0 ( 2 ) v note: 2. operating at high v in can create excessive ac overshoots on the vswh - to - gnd and boot - to - gnd nodes during mosfet switching transients . for reliable drmos operation, vswh - to - gnd and boot - to - gnd must remain at or below the absolute maximum rating s shown in the table above . refer to the application information and pcb layout guidelines sections of this datasheet for additional information .
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 . 1 fdmf6 82 4 c extra - small, high - performance, high - frequency drmos module electrical characteristics typical values are v in = 12 v, v cin = 5 v, v drv = 5 v, and t a = t j = +25c unless otherwise noted. symbol parameter condition min. typ. max. unit basic operation i q quiescent current i q =i vcin +i vdrv , pwm=lo w or hi gh or float 2 ma v uvlo uvlo threshold v cin r ising 2.9 3. 1 3.3 v v uvlo _hys uvlo hysteresis 0. 4 v pwm input ( v cin = v drv = 5 v 10%) r up_pwm pull - up impedance v pwm =5 v 10 k r d n _pwm pull - down impedance v pwm =0 v 1 0 k v ih_pwm pwm high level voltage 3.04 3.5 5 4.05 v v tri_hi 3 - state upper threshold 2.95 3.45 3.94 v v tri_lo 3 - state lower threshold 0.98 1.2 5 1.52 v v il_pwm pwm low level voltage 0.84 1.1 5 1.42 v t d_hold - off 3 - state shut - o ff time 1 6 0 200 ns v hiz_pwm 3 - state open voltage 2.20 2.50 2.80 v pwm input (v cin = v drv = 5 v 5%) r up_pwm pull - up impedance v pwm =5 v 10 k r d n _pwm pull - down impedance v pwm =0 v 1 0 k v ih_pwm pwm high level voltage 3.22 3.5 5 3.87 v v tri_hi 3 - state upper threshold 3.13 3.45 3.77 v v tri_lo 3 - state lower threshold 1.04 1.2 5 1.46 v v il_pwm pwm low level voltage 0.90 1.1 5 1.36 v t d_hold - off 3 - state shut - o ff time 1 6 0 200 ns v hiz_pwm 3 - state open voltage 2.30 2.50 2.70 v disb# input v ih_ disb high - level input voltage 2 v v il_ disb low - level input voltage 0.8 v i pld pull - down current 10 a t pd_ disb l propagation delay pwm=gnd, delay between disb# from high to low to gl from high to low 25 ns t pd_ disb h propagation delay pwm=gnd, delay between disb# from low to high to gl from low to high 25 ns smod # input v ih_ smod high - level input voltage 2 v v il_ smod low - level input voltage 0.8 v i pl u pull - up current 10 a t pd_ s lgll propagation delay pwm=gnd, delay between smod # from high to low to gl from high to low 10 ns t pd_ s hglh propagation delay pwm=gnd, delay between smod # from low to high to gl from low to high 10 ns continued on the following page
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 . 1 fdmf6 82 4 c extra - small, high - performance, high - frequency drmos module electrical characteristics typical values are v in = 12 v, v cin = 5 v, v drv = 5 v, and t a = t j = +25c unless otherwise noted. symbol parameter condition min. typ. max. unit thermal warning flag t act activation temperature 150 c t rst reset temperature 135 c r thwn pull - down resistance i pld =5 ma 3 0 high - side driver ( f sw = 1000 khz, i out = 30 a, t a = +25 c) r source_gh output impedance, sourcing source current=100 ma 1 r sink_gh output impedance, sinking sink current=100 ma 0.8 t r_gh rise time gh = 10% to 90% 10 ns t f_gh fall time gh = 90% to 10% 10 ns t d_deadon ls to hs deadband time gl g oing low to gh going high, 1 .0 v gl to 10 % gh 15 ns t pd_plghl pwm low propagation delay pwm g oing low to gh g oing low, v il_pwm to 90% gh 20 3 0 ns t pd_phghh pwm high propagation delay ( smod # =0 ) pwm g oing high to gh g oing high, v ih_pwm to 10% gh ( smod # = 0, i d_ls >0 ) 30 ns t pd_tsghh exiting 3 - state propagation delay pwm ( f rom 3 - state) g oing high to gh g oing high, v ih_pwm to 10% gh 3 0 ns low - side driver ( f sw = 1000 khz, i out = 30 a, t a = +25 c) r source_gl output impedance, sourcing source current=100 ma 1 r sink_gl output impedance, sinking sink current=100 ma 0. 5 t r_gl rise time gl = 10% to 90% 20 ns t f_gl fall time g l = 90% to 10% 10 ns t d_deadoff hs to ls deadband time sw going low to gl g oing high, 2 . 2 v sw to 10% gl 15 ns t pd_phgll pwm - high propagation d elay pwm going high to gl g oing low, v ih_pwm to 90% gl 10 25 ns t pd_tsglh exiting 3 - state propagation delay pwm (from 3 - state) going low to gl g oing high, v il_pwm to 10% gl 2 0 ns boot diode v f forward - voltage drop i f = 20 ma 0. 3 v v r breakdown voltage i r =1 ma 22 v
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 . 1 fdmf6 82 4 c extra - small, high - performance, high - frequency drmos module timing diagram figure 5. pwm timing diagram t d_deadon pwm v sw h gh to v sw h gl t pd_phgll t d_deadoff v ih_pwm v il_pwm 90% 90% 1 . 0 v 10% t pd_plghl 10% 1. 2 v 2.2v
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 . 1 fdmf6 82 4 c extra - small, high - performance, high - frequency drmos module typical performance characteristic s test conditions: v in =12 v, v out =1 v, v cin =5 v, v drv =5 v, l out = 25 0 nh, t a =25c, and natural convection cooling, unless otherwise specified. figure 6. safe operating area figure 7. power loss vs. output current figure 8. p ower loss vs. switching frequency figure 9. power loss vs. input voltage figure 10. power loss vs. driver supply voltage figure 11. power loss vs. output voltage 0 5 10 15 20 25 30 35 40 45 50 0 25 50 75 100 125 150 module output current, i out (a) pcb temperature, t pcb ( c) f sw = 300khz f sw = 1000khz v in = 12v, v drv & v cin = 5v, v out = 1v 0 1 2 3 4 5 6 7 8 9 10 11 0 5 10 15 20 25 30 35 40 45 module power loss, pl mod (w) module output current, i out (a) 300khz 500khz 800khz 1000khz v in = 12v, v drv & v cin = 5v, v out = 1v 0.9 1.0 1.1 1.2 1.3 1.4 1.5 100 200 300 400 500 600 700 800 900 1000 1100 normalized module power loss module switching frequency, f sw (khz) v in = 12v, v drv & v cin = 5v, v out = 1v, i out = 30a 0.98 1.00 1.02 1.04 1.06 1.08 4 6 8 10 12 14 16 18 normalized module power loss module input voltage, v in (v) v drv & v cin = 5v, v out = 1v, f sw = 300khz, i out = 30a 0.90 0.95 1.00 1.05 1.10 1.15 4.0 4.5 5.0 5.5 6.0 normalized module power loss driver supply voltage, v drv & v cin (v) v in = 12v, v out = 1v, f sw = 300khz, i out = 30a 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 normalized module power loss module output voltage, v out (v) v in = 12v, v drv & v cin = 5v, f sw = 300khz, i out = 30a
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 . 1 fdmf6 82 4 c extra - small, high - performance, high - frequency drmos module typical performance characteristic s test conditions: v in =12 v, v out =1 v, v cin =5 v, v drv =5 v, l out = 25 0 nh, t a =25c, and natural convection cooling, unless otherwise specified. figure 12. power loss vs. output inductor figure 13. driver supply current vs. switching frequency figure 14. driver supply current vs. driver supply voltage figure 15. driver supply current vs. output current figure 16. uvlo threshold vs. temperature figure 17. pwm threshold vs. driver supply voltage 0.96 0.97 0.98 0.99 1.00 1.01 200 250 300 350 400 450 500 normalized module power loss output inductor, l out (nh) v in = 12v, v drv & v cin = 5v, f sw = 300khz, v out = 1v, i out = 30a 5 10 15 20 25 30 35 40 45 100 200 300 400 500 600 700 800 900 1000 1100 driver supply current, i drv & i cin (ma) module switching frequency, f sw (khz) v in = 12v, v drv & v cin = 5v, v out = 1v, i out = 0a 10 11 12 13 14 15 16 17 4.0 4.5 5.0 5.5 6.0 driver supply current, i drv & i cin (ma) driver supply voltage, v drv & v cin (v) v in = 12v, v out = 1v, f sw = 300khz, i out = 0a 0.98 0.99 1.00 1.01 1.02 1.03 1.04 0 5 10 15 20 25 30 35 40 45 normalized driver supply current module output current, i out (a) v in = 12v, v drv & v cin = 5v, v out = 1v f sw = 300khz f sw = 1000khz 2.6 2.7 2.8 2.9 3.0 3.1 3.2 - 55 0 25 55 100 125 150 driver ic supply voltage, v cin (v) driver ic junction temperature, t j ( o c) uvlo up uvlo dn 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 4.50 4.75 5.00 5.25 5.50 pwm threshold voltage, v pwm (v) driver ic supply voltage, v cin (v) v ih_pwm t a = 25 c v tri_hi v tri_lo v il_pwm v hiz_pwm
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 . 1 fdmf6 82 4 c extra - small, high - performance, high - frequency drmos module typical performance characteristic s test conditions: v cin =5 v, v drv =5 v, t a =25c, and natural convection cooling, unless otherwise specified. figure 18. pwm threshold vs. temperature figure 19. smod # threshold vs. driver supply voltage figure 20. smod # threshold vs. temperature figure 21. smod # pull - up current vs. temperature figure 22. disb # threshold vs. driver supply voltage figure 23. disb # threshold vs. temperature 1.2 1.4 1.6 1.8 2.0 2.2 4.50 4.75 5.00 5.25 5.50 disb# threshold voltage, v disb (v) driver ic supply voltage, v cin (v) v ih_disb# v il_disb# t a = 25 c 1.2 1.4 1.6 1.8 2.0 2.2 - 55 0 25 55 100 125 150 disb# threshold voltage, v disb (v) driver ic junction temperature, t j ( o c) v ih_disb# v il_disb# v cin = 5v 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 - 55 0 25 55 100 125 150 pwm threshold voltage, v pwm (v) driver ic junction temperature, t j ( o c) v cin = 5v v ih_pwm v tri_hi v hiz_pwm v tri_lo v il_pwm 1.2 1.4 1.6 1.8 2.0 2.2 4.50 4.75 5.00 5.25 5.50 smod# threshold voltage, v smod (v) driver ic supply voltage, v cin (v) v ih_smod# v il_smod# t a = 25 c 1.2 1.4 1.6 1.8 2 2.2 - 55 0 25 55 100 125 150 smod# threshold voltage, v smod (v) driver ic junction temperature, t j ( o c) v ih_smod# v il_smod# v cin = 5v - 12.0 - 11.5 - 11.0 - 10.5 - 10.0 - 9.5 - 9.0 - 55 0 25 55 100 125 150 smod# pull - up current, i plu (ua) driver ic junction temperature, t j ( o c) v cin = 5v
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 . 1 fdmf6 82 4 c extra - small, high - performance, high - frequency drmos module typical performance characteristic s test conditions: v cin =5 v, v drv =5 v, t a =25c, and natural convection cooling, unless otherwise specified. figure 24. disb # pull - down current vs. temperature figure 25. boot diode forward voltage vs. temperature 9.0 9.5 10.0 10.5 11.0 11.5 12.0 - 55 0 25 55 100 125 150 disb# pull - down current, i pld (ua) driver ic junction temperature, t j ( o c) v cin = 5v 100 150 200 250 300 350 400 450 500 - 55 0 25 55 100 125 150 boot diode forward voltage, v f (mv) driver ic junction temperature, t j ( o c) i f = 20ma
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 . 1 fdmf6 82 4 c extra - small, high - performance, high - frequency drmos module functional description the fdmf 682 4 c is a driver - plus - fet module optimized for the synchronous buck converter topology. a single pwm input signal is all that is required to properly drive the high - side and the low - side mosfets. each part is capable of driving speeds up to 1 mhz. vcin and disable (disb#) the vcin pin is monitored by an u nder - v oltage l ockout (uvlo) circuit . when v ci n rises above ~3. 1 v, the driver is enabled. when v c in falls below ~2. 7 v, the driver is disabled (gh, gl = 0). the driver can also be disabled by pulling the disb# pin low (disb# < v il_ disb ), which holds both gl and gh low regardless of the pwm input state. the driver can be enabled by raising the disb# pin voltage high (disb# > v ih_ disb ). table 1. uvlo and disable logic uvlo disb# driver state 0 x disabled (g h , gl = 0 ) 1 0 disabled (g h , gl = 0 ) 1 1 enabled ( s ee table 2 ) 1 open disabled (g h , gl = 0 ) note: 3. disb# internal pull - down current source is 10 a. thermal warning flag (thwn#) the fdmf 682 4 c provides a thermal warning flag (thwn # ) to warn of over - temperature conditions. the thermal warning flag uses an open - drain output that pull s to cgnd when the activation temperature (150c) is reached. the thwn # output return s to a high - impedance state once the temperature falls to the reset temperature (135c) . for use, t he thwn # output requires a pull - up resistor, which can be connected to vcin. thwn # does not disable the drmos module. figure 26. thwn o peration three - s tate pwm input the fdmf 682 4 c incorporates a three - state 5 v pwm input gate drive design. the t hree - state gate drive has both logic high level and low level , along with a three - state shutdown window. when the pwm input signal enters and remains within the three - state window for a defined hold - off time (t d_hold - off ), both gl and gh are pulled low . this enables the gate drive to shut down both high - side and low - s ide mosfets to support fe atures such as phase shedding, which is common on multi - phase voltage regulators. e xiting three - s tate c ondition when exiting a valid three - state condition, the fdmf 682 4 c follows the pwm input command. if the pwm input goes from three - state to low , the low - side mosfet is turned on. i f the pwm input goes from three - state to high , the high - side mosfet is turned on . this is illustrated in figure 27 . the fdmf 682 4 c design allows for short propagation delays when exiting the three - state window (see electrical characteristics) . low - side driver the low - side driver (gl ) is designed to drive a ground - referenced , low - r ds(on) , n - c hannel mosfet. the bias for gl is internal ly connected between the vdrv and cgnd pins . when the driver is enabled, the driver's output is 180 out of phase with the pwm input. when the driver is disabled (disb# = 0 v), gl is held low . high - side driver the high - side driver (gh) is designed to drive a floating n - c hannel mosfet. the bias voltage for the high - side driver is developed by a bootstrap supply circuit consisting of the internal schottky diode and external bootstrap capacitor (c boot ). during start up, v swh is held at pgnd, allowing c boot to charge to v drv through the internal diode. when the pwm input goes high , gh begin s to charge the gate of the high - side mosfet (q1). during this transition, the charge is removed from c boot and delivered to the gate of q1. as q1 turns on, v swh rises to v in , forcing the boot pin to v in + v boot , which provide s sufficient v gs enhancement for q1. to complete the switching cycle, q1 is turned off by pulling gh to v swh . c boot is then recharged to v drv when v swh falls to pgnd. gh output is in - phase with the pwm input. the high - side gate is held low when the driver is disabled or the pwm signal is held within the three - state window for longer than the three - state hold - off time, t d_hold - off . 1 5 0 c activation temperature t j_driver ic thermal warning normal operation h igh l ow 1 3 5c reset temperature thwn # logic state
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 . 1 fdmf6 82 4 c extra - small, high - performance, high - frequency drmos module adaptive gate drive circuit the driver ic advanced design ensures minimum mosfet dead - time , whi le eliminating potential shoot - t hrough (cross - conduction) currents. it senses the state of the mosfets and adjusts the gate drive adaptively to ensure they do not conduct simultaneous ly . figure 27 provides the relevant timing waveforms. to prevent overlap during the low - to - high switching transition (q2 off to q1 on ), the adaptive circuitry monitors the voltage at the gl pin . when t he pwm signal goes high, q2 begins to turn off after a propagation delay (t pd_phgll ). once the gl pin is discharged below 1 . 0 v, q1 begins to turn on after adaptive delay t d_deadon . to pre clude overlap during the high - to - low transition (q1 off to q2 on ), the adaptive circuitry monitors the voltage at the gh - to - phase pin pair . when the pwm signal goes low, q1 begins to turn off after a propagation delay (t pd_plghl ). once the voltage across gh - to - phase falls below 2 . 2 v, q2 begins to turn on afte r adaptive delay t d_deadoff . figure 27. pwm and 3 - statetiming diagram t pd_tsghh vswh gh to v swh gl t pd_phgll t d_ hold - off 90% exit 3 - state 1.0v pwm v il_pwm v ih_pwm v tri_hi v ih_pwm v ih_pwm 1 0% t r_gl t d_ hold - off exit 3 - state v ih_pwm v tri_hi v tri_lo v il_pwm t pd_plghl t pd_tsghh dcm t f_gh t r_gh t d_ hold - off 1 0% ccm dcm exit 3 - state 9 0% 1 0% 9 0% enter 3 - state enter 3 - state t d_deadoff t d_deadon enter 3 - state t f_gl v in v out 2.2v t pd_tsglh notes : t pd_xxx = propagation delay from external signal (pwm, smod# , etc.) to ic generated signal. example (t pd_phgll C pwm going high to ls v gs (gl) going low ) t d_xxx = delay from ic generated signal to ic generated signal. example (t d_deadon C ls v gs (gl) low to hs v gs (gh) high ) pwm exiting 3 - state t pd_phgll = pwm rise to ls v gs fall, v ih_pwm to 90% ls v gs t pd_tsghh = pwm 3 - state to high to hs v gs rise, v ih_pwm to 10% hs v gs t pd_plghl = pwm fall to hs v gs fall, v il_pwm to 90% hs v gs t pd_tsglh = pwm 3 - state to low to ls v gs rise, v il_pwm to 10% ls v gs t pd_phghh = pwm rise to hs v gs rise, v ih_pwm to 10% hs v gs ( smod # held low ) smod# dead times t pd_ s lgll = smod# fall to ls v gs fall, v il_ smod to 90% ls v gs t d_deadon = ls v gs fall to hs v gs rise, ls - comp trip value (~1. 0 v gl) to 10% hs v gs t pd_ s hglh = smod# rise to ls v gs rise, v ih_ smod to 10% ls v gs t d_deadoff = v sw h fall to ls v gs rise, sw - comp trip value (~ 2 . 2 v vswh ) to 10% ls v gs
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 . 1 fdmf6 82 4 c extra - small, high - performance, high - frequency drmos module skip mode ( smod # ) the skip mode function allows for higher converter efficiency when operated in light - load conditions. when smod # is pulled low , the low - side mosfet gate signal is disabled (held low), prevent ing dis charg e of the output capacitors as the filter inductor current atte mpts reverse current flow C known as d iode e mulation mode . when the smod # pin is pulled high , the synchronous buck converter works in s ynchronous m ode . this mode allows for gating on the low side mos fet . when the smod# pin is pulled low, the low - side mosfet is gated off. if the smod# pin is connected to the pwm controller , the controller can actively e nable or disable smod# when the controller detects light - load condition from output current sensing. normally this pin is a ctive low . see figure 28 for timing delays . table 2. smod# logic disb# pwm smod# gh gl 0 x x 0 0 1 3 - state x 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 note: 4. the smod# feature is intended to have a short propagation delay between the smod# signal and the low - side fet v gs response time to control diode emulation on a cycle - by - cycle basis. figure 28. smod # timing diagram t d_deadon pwm v sw h gh to v sw h gl t pd_phgll t pd_plghl t d_deadoff v ih_pwm v il_pwm 90% 1 0% 90% 1.0v 2.2v t pd_phghh t pd_shglh delay from smod# going high to ls v gs high hs turn - on with smod# low smod# t pd_slgll delay from smod# going low to ls v gs low dcm ccm ccm 1 0% v ih_pwm 1 0% v out v ih_smod v il_smod 1 0%
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 . 1 fdmf6 82 4 c extra - small, high - performance, high - frequency drmos module application information supply capacitor selection for the supply inputs (v cin ), a local ceramic bypass capaci tor is re commende d to reduce noise and to supply the peak current. u se at least a 1 f x7r or x5r capacitor . keep this capacitor close to the vcin pin and connect it to the gnd plane with vias. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c boot ), as shown in figure 30 . a bootstrap capacitance of 100nf x7r or x5r capacitor is usua lly adequate. a series bootstrap resistor may be needed for specific applications to improve switchin g noise immunity. the boot resistor may be required when operating above 15 v in and is effective at controlling the high - side mosfet turn - on slew rate and v shw overshoot. r boot values from 0.5 to 3.0 are typically effective in reducing vswh overshoot. vcin filter the vdrv pin provides powe r to the gate drive of the high - side and low - side power mos fet . in most cases, it can be connected directly t o vcin, the pin that provides power to the logic section of the driver. for additional noise immunity, an rc filter can be inserted between the vdrv and vcin pins . recommended values would be 10 and 1 f. power loss and efficiency measurement and calculation refer to figure 30 for power loss testing method. power loss calculations are: p in =(v in x i in ) + (v 5v x i 5 v ) (w) (1) p sw =v sw x i out (w) ( 2 ) p out =v out x i out (w) ( 3 ) p loss_module =p in - p sw (w) ( 4 ) p loss_board =p in - p out (w) ( 5 ) eff module =100 x p sw /p in (%) ( 6 ) eff board =100 x p out /p in (%) ( 7 ) figure 29. block diagram with v cin f ilter figure 30. power loss measurement vdrv vcin vin pwm v 5v disb# pwm input off on c vdrv c vin c boot r boot l out c out a i 5v a i in v in v v sw a i out thwn # boot vswh cgnd pgnd disb# fdm f 67 0 5 open - drain output phase smod# c v cin r v cin fdmf 682 4 c v out v 5 v d i s b # p w m i n p u t o f f o n c v d r v c v i n c b o o t r b o o t l o u t c o u t v i n f d m f 6 8 2 4 c o p e n - d r a i n o u t p u t v d r v v c i n v i n p w m t h w n # b o o t c g n d p g n d d i s b # p h a s e s m o d # c v c i n v o u t v s w h r v c i n a a a v i 5 v i i n i o u t v s w
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 . 1 fdmf6 82 4 c extra - small, high - performance, high - frequency drmos module pcb layout guidelines figure 31 and figure 32 provide an example of a proper layout for the fdmf 682 4 c and critical components. all of the high - current paths, such as vin, vswh, vout, and gnd copper, should be short and wide for low inductance and resistance. this aids in achiev ing a more stable and evenly distributed current flow, along with enhanced heat radiation and system performance. r ecommendations for pcb d esigner s 1. input ceramic bypass capacitors must be placed close to the vin and pgnd pins. this help s reduce the high - curre nt power loop inductance and the input current ripple induced by the p ower mosfet switching operation. 2. the v swh copper trace serves two purposes . in addition to being the high - frequency current path from the drmos package to the output inductor, it serves as a heat sink for the low - side mosfet in the drmos package. the trace should be short a nd wide enough to present a low - impedance path for the high - frequency, high - current flow between the drmos and inductor . the short and wide trace minimize s electrical l osses as well as the drmos temperature rise. n ote that the v swh node is a high - voltage and high - frequency switching node with high noise potential. care should be taken to minimize coupling to adjacent traces. s ince this copper trace acts as a heat sink fo r the lower mos fet, balance using the largest area possible to improve drmos cooling while maintaining acceptable noise emission. 3. an o utput inductor should be located close to the fdmf 682 4 c to minimize the power loss due to t he v swh copper trace. c are shou ld also be taken so the inductor dissipation does not heat the drmos. 4. powertrench ? mosfets are used in the output stage and are effective at minimizing ringing due to fast switching. in most cases, no vswh snubber is required. if a snubber is used, it should be placed close to the vswh and pgnd pins. the selected resistor and capacitor need to be the proper size for power dissi pation. 5. vcin, vdrv , and boot capacitors should be placed as close as possible to the vcin - to - cgnd, vdrv - to - cgnd, and boot - to - phase pin pairs to ensure clean and stable power. routing width and len gth should be considered as well . 6. incl ude a trace from the p hase pin to the vswh pin to improve noise margin. keep th is trace as short as possible. 7. the layout should inclu de the option to insert a small - value series boot resistor between the boot c apacitor and boot pin. the boot - loop size, including r boot and c boot , should be as small as possible. the boot resistor may be required when operating above 15 v in and is ef fective at controlling the high - side mosfet turn - on slew rate and v shw overshoot. r boot can improve noise operating margin in synchronous buck designs that may have noise issues due to ground bounce or high positive and negative v swh ringing. i nserting a boot resistance lower s the drmos efficiency. efficiency versus noise trade - offs must be considered. r boot values from 0.5 ? to 3 .0 ? are typically effec tive in redu cing v swh overshoot . 8. the vin and pgnd pins handle large current transients with frequency components greater than 100 mhz. if possible, these pins should be connected directly to t he vin and board gnd planes. the use of thermal relief traces in series with these pins is discouraged since this adds inductance to the power path. this added inductance in series with either the vin or pgnd pin degrades system noise immunity by increasin g positive and negative v swh ringing. 9. gnd pad and pgnd pins should be connected to the gnd copper plane with multiple vias for stable grounding. poor grounding can create a noise transient offset voltage level between cgnd and pgnd. this could lead to faul ty operation of the gate driver and mosfet s . 10. ringing at the boot pin is most effectively controlled by close placement of the boot capacitor. do not add an additional boot to the pgnd capacitor. this may lead to excess current flow through the boot diode. 11. the smod # and disb# pins have weak internal pull - up and pull - down current sources, respectively. these pins should not have any noise filter capacitors. do not to float these pins unless absolutely necessary . 12. use multiple vias on the vin and vout copper areas to interconnect top, inner, and bottom layers to distribute current flow and heat conduction. do not put many vias on the vswh copper to avoid extra parasitic inductance and no ise on the switching waveform. as long as efficiency and thermal performan ce are acceptable, place only one vswh copper on the top layer and use no vias on the vswh copper to minimize switch node parasitic noise. vias should be relatively large and of reasonably low inductance. critical high - frequency components, such as r boot , c boot , rc snubber, and bypass capacitors; should be located as close to the respective drmos module pins as possible on the top layer of the pcb. if this is not feasible, they can be connected from the backside through a network of low - inductance vias.
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 . 1 fdmf6 82 4 c extra - small, high - performance, high - frequency drmos module figure 31. pcb layout example (top view) figure 32. pcb layout example (bottom view)
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 . 1 fdmf6 82 4 c extra - small, high - performance, high - frequency drmos module physical dimensions figure 33. 40 - lead, clipbond pqfn drmos, 6.0 x 6.0 mm package package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to v erify o r obtain the most recent revision. package specifications do not expand the terms of fairchilds worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . bottom view land pattern recommendation notes: unless otherwise specified a) does not fully conform to jedec registration mo-220, dated may/2005. b) all dimensions are in millimeters. c) dimensions do not include burrs or mold flash. mold flash or burrs does not exceed 0.10mm. d) dimensioning and tolerancing per asme y14.5m-1994. e) drawing file name: pqfn40arev3 see detail 'a' detail 'a' scale: 2:1 seating plane 0.65 0.40 2.10 0.50 typ 4.50 5.80 2.50 0.25 1.60 0.60 0.15 2.10 0.35 1 top view front view c 0.30 0.20 0.05 0.00 1.10 0.90 0.10 c 0.08 c 10 11 20 21 30 31 40 0.40 0.50 (0.70) 0.40 2.000.10 2.000.10 (0.20) (0.20) 1.500.10 0.50 0.30 (40x) 0.20 6.00 6.00 0.10 c 2x b a 0.10 c 2x 0.30 0.20 (40x) 4.400.10 0.10 c a b 0.05 c (2.20) 0.50 10 1 40 31 30 21 20 11 pin#1 indicator pin #1 indicator may appear as optional 2.400.10
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FDMF6824C ? rev. 1 . 0 . 1 fdmf6 82 4 c extra - small, high - performance, high - frequency drmos module

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